Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science
6.111 - Introductory Digital Systems Laboratory
Introduction
The term project in 6.111 is your opportunity to specify a small digital
system. You will then design, build, debug, demonstrate, and report on
this system. The purpose of this memorandum is to set forth our
expectations and requirements for this project and to make a few
suggestions which should help to make your project a success.
In order to accomplish all that is expected by the end of the term, it
is essential that you stay on schedule.
Both the determination of grades and the project time requirements are
inherently subjective. Lab 4 provides some guidance to the evaluation
of project size and complexity. Lab 4 requires almost a full kit's
worth of components. A reasonable guideline as to size of 6.111
projects is that it not require more than a kit and a proto board per
person.
6.111 student projects often become too large because of a desire to
effect computations in parallel and at high speed. Data paths are often
unnecessarily wide and redundant. It is generally far better to
minimize the type and extent of the data paths even though this results
in more complicated control circuitry.
Use of microprogrammed sequencers and FSMs implemented with PALs allows
implementation of complicated control with a small number of ICs.
Please remember that massive data paths that enable computation at
speeds far faster than needed do not represent a good design! It is
almost always better to spend more time thinking and less time wiring.
Instructions
1. The first step in starting your project is to find
a partner with whom you wish to work. Two-person projects are preferred,
but three-person projects are permitted. Individual projects must be
approved by the lecturer.
2. The second step is to decide what you wish to do. A
list of project suggestions appears in this handout. This list may be
helpful in this regard since it is compiled from past projects which were
successfully completed.
3. The third step is to submit a PROPOSAL ABSTRACT
(one for each student) using the attached form. This item and the
PROPOSAL which follows are to be prepared jointly with your partner. We
will use the proposal abstract to assign project teams to members of the
teaching staff. Those assignments will be posted shortly after the
deadline for proposal submission.
4. The fourth step is to submit the PROPOSAL. It is
comprised of:
The project should be partitioned into two separately testable
subsystems. Each subsystem is to be the responsibility of a single
partner.
The proposal should be typewritten. Typically, it should be two to five
pages in length, single-spaced, plus the block diagram and any figures
you may need.
5. The fifth step is the Proposal Conference, which is
scheduled immediately following the due date for the Proposal. Each
project Proposal must be presented orally to the Staff so that both you
and we understand what it is you are attempting, and whether your basic
design approach is sound. Each project group should sign up for a 30
minute session. Sign-up sheets will be posted in the lab in advance of
the first day of presentations. Be sure to bring extra copies of your
Proposal with you to the presentation so that TA's can follow your talk
without your having to draw your block diagram on the chalkboard.
6. The sixth step is to prepare detailed Module
Designs and Logic Diagrams for each of the blocks in the block diagram,
and have these approved by your project TA.
7. The seventh step is to build, debug and test your system. Project CONSTRUCTION may not begin until you have:
8. The eighth step is to demonstrate your project to
a member of the Staff. It is likely we will want to videotape your
presentation.
9. The ninth step is to complete and submit the
PROJECT REPORT. Material from the proposal can be used. The report may
be prepared jointly:
See the Report Guide handout for general requirements for the
Final Project Report.
10. The final step is to turn in your kit and other
components. Remove all wires from the socket strips and return the
chips to their places in the box.
Schedule
Pertinent due dates are as follows:
Formation of Project Teams Wednesday, October 15, 1997Project Abstracts Monday, October 20, 1997
Proposal Conference Friday, October 31, 1997
Logic Conference Friday, November 7, 1997
Last Day to Add 6.905 Wednesday, November 19, 1997
Project Demonstrations Tuesday, December 9, 1997
Project Reports Wednesday, December 10, 1997 (5:00 PM)
Extra Units for ``Large'' 6.111 Projects
Most 6.111 students spend more hours per week than warranted by the
12 unit rating. Primarily this is due to large final projects. It
is now possible to register for an additional 6 units of credit for
6.111.
Our motivation for enabling the availability of these extra units is
two-fold. Foremost is our desire to convince 6.111 students that
they need NOT do a project which is bigger and more complicated than
ever done in the past. Secondly, recognizing that many students will
continue to do ambitious projects, we would like to credit 6.111
students with units appropriate to work expended.
We are concerned that the availability of extra units may be taken as
a signal to escalate the size of 6.111 projects. Indeed, if we
perceive this to be the result, we may discontinue this proecdure.
While a large project is not required for the extra units, timely
completion of coursework is. Before you can register for the extra
units, you must have completed all of the labs and homework
assignments, submitted your proposal, had your design conference and
received clearance to begin construction from your project TA.
Procedures for adding six extra units (as 6.919) are described on an
attached page, together with additional information.
Project Resources
Project resources are allocated on a per student basis. This means that
a two person project has twice the resources that an individual project
has, etc. You have already been issued a kit and a quantity of ICs. The
following items are available on an individual signout basis. Note that
the quantities listed must suffice for the entire class.
| Quantity | Item * Indicates a buy to replace breakage |
| *200 | Proto-boards which do not have switches, lights, or power supplies. Suitable 5 volt power supplies are mounted on the lab benches. Each proto-board will hold about one-half the number of ICs that can be mounted on your kit. |
| *100 | 50 pin 3M ribbon cables for kit to kit connections |
The following items may have to be shared. Cables for the TVs,
Z19s, and HP Displays must be signed out and returned daily.
| 14 | Z19 Video Display Terminals with RS 232 cable |
| 8 | HP XY Displays with coax cable set |
| 15 | Monochrome TV Monitors with BNC cable |
| 15 | Color TV Monitors with cable |
| 2 | HP Pen Plotters with RS 232 cable |
| 25 | Speakers (with built in amplifier) |
| 10 | Microphone (with built in preamplifier) |
| 2 | Television Cameras with sync |
| 2 | Digital shaft encoders |
| 6 | Stepper Motors |
The following items may be signed out from the instrument room.
Data sheets are available from the instrument room.
| *10 | MC10319L | Flash A to D Converters |
| *50 | LM386 | Low Power Audio Amplifiers |
| *50 | 10 Mhz Crystal Oscillators | |
| *50 | MC6847 | Video Display Generators |
| *50 | 3.575945 MHz Crystals | |
| *50 | 2K Pots | |
| *50 | AY 1015D | UARTs |
| *50 | 1488 | TTL to RS 232 Driver |
| *50 | 1489 | RS 232 to TTL Receivers |
| *50 | 741 | Op Amps |
| *25 | LF357 | Op Amps |
| *25 | LM311 | Comparators |
| *50 | AM26LS32 | Line Receivers (Comparators) |
| *50 | AD558JN | D to A Converter |
| *100 | AD670JN | A to D Converter |
| *100 | 29C10A | Micro Sequencer |
| *50 | 898-1-R5.1K | (or 898-1-R4.7K) resistor packs |
| 50 | LED Assemblies | |
| 150 | HEX LEDs | |
| 40 | AM25S557 | High Speed 8 x 8 Multipliers |
| 20 | AM25S558 | High Speed 8 x 8 Multipliers |
| *50 | AM29C509DC | High Speed 12 x 12 Multiplier Accumulator |
| *50 | 6850 | Asynchronous Communications Interface Adapter |
| *10 | 6N138 | Opto-isolater plus 1N914 diode |
| *10 | 5-pin DIN cables (female cable to wires) | |
| small | misc. resistors and capacitors | |
| *100 | 74LS00 | Quad 2-input NAND gate |
| *75 | 74LS02 | Quad 2-input NOR gate |
| 75 | 74LS03 | Quad 2-input NOR open collector gate |
| *160 | 74LS04 | Hex inverter |
| *100 | 74LS08 | Quad 2-input AND gate |
| *120 | 74LS10 | Triple 3-input NAND gate |
| *50 | 74LS14 | Hex Schmitt Trigger INVERTER |
| *50 | 74LS20 | Dual 4-input AND gate |
| 50 | 74LS30 | 8-input NAND gate |
| *50 | 74LS32 | quad 2-input OR gate |
| *50 | 74LS37 | quad 2-input NAND buffer |
| *50 | 74S38 | quad 2-input NAND open collector gate |
| *25 | 74LS42 | BCD to Decimal decoder |
| *100 | 74LS47 | BCD to 7-segment decoder driver |
| *150 | 74LS74 | Dual D flip flop |
| *150 | 74LS85 | 4-bit comparator |
| *50 | 74LS86 | quad 2-input XOR gate |
| 50 | 74LS107 | dual JK flip flop with clear |
| *50 | 74LS112 | dual JK flip flop with preset and clear |
| *50 | 74LS123 | dual retriggerable monostable |
| 75 | 74LS126 | quad tri-state noninverting buffer |
| *50 | 74LS133 | 13-input NAND gate |
| *75 | 74LS138 | 3 to 8 decoder |
| *75 | 74LS139 | dual 2 to 4 decoder |
| *50 | 74150 | 16 to 1 multiplexor |
| *150 | 74LS151 | 8 to 1 multiplexor |
| *100 | 74LS153 | dual 4 to 1 multiplexor |
| 150 | 74LS157 | quad 2 to 1 multiplexor |
| *300 | 74LS161 | binary 4-bit counter with direct clear |
| *500 | 74LS163 | binary 4-bit counter with synchronous clear |
| *100 | 74LS169 | 4-bit up/down counter |
| 100 | 74LS175 | quad D edge triggered FF with clear, Q, /Q |
| *50 | 74LS181 | 4-bit ALU |
| 25 | 74LS193 | binary dual clock up/down counter with clear |
| *100 | 74LS194 | 4-bit bidirectional shift register |
| *300 | 74LS244 | Octal tri-state noninverting buffer |
| *100 | 74LS245 | Octal tri-state bidirectional bus buffers |
| *200 | 74LS257 | quad 2 to 1 tri-state multiplexor |
| *100 | 74LS259 | 8-bit addressable latch (positive output decoder) |
| 150 | 74LS273 | Octal D edge triggered flip flop with clear |
| *100 | 74LS283 | 4-bit adder |
| 100 | 74LS367 | Hex tri-state noninverting buffer |
| 100 | 74LS368 | Hex tri-state inverting buffer |
| 75 | 74LS373 | Octal D tri-state latches |
| *100 | 74LS374 | Octal D edge triggered tri-state flip flop |
| *200 | 74LS377 | Octal D edge triggered flip flop with enable |
| *100 | 74LS393 | Dual 4-bit binary counters |
| *100 | 74LS399 | quad 2-input multiplexors with storage |
| *25 | 74LS670 | 4 by 4 register file |
| small | Misc. | Crystal Oscillators |
| Many | 28F256A | FLASH Memory |
| 100 | Am28F010 | 131,072 x 8-Bit CMOS Flash Memory |
| 100 | Am28F020 | 262,144,072 x 8-Bit CMOS Flash Memory |
| 100 | Am28F512 | 65,536 x 8-Bit CMOS Flash Memory |
| *400 | 2716 | 2K by 8 EPROM |
| *100 | 2732 | 4K by 8 EPROM |
| *100 | 2764 | 8K by 8 EPROM |
| *100 | 6116-3 | 2K by 8 SRAM |
| *200 | 6264-15 | 8K by 8 SRAM |
| *50 | 62256-12 | 32K by 8 SRAM |
| Many | AMD PALS | 16L8, 16R4, 16R6, and 16R8 |
| Many | Fairchild PALS | 16P8, 16RP4, 16RP6, and 16RP8 |
| 200 | 22V10 PALS | |
| *400 | 16V8 PALS | |
| *400 | 20V8 PALS | |
| 200 | ep300 PALS | |
| 300 | 5C060 PALS | |
| *25 | MAXIM 233 | RS 232 level converters |
| *25 | Am29C517APC | 16 bit multiplier |
| *25 | 54ACT/74ACT715 | Programmable Video Sync Generator |
| *25 | GS4981 | Monolithic Video Sync Separator |
| *25 | CD22204 | Harris 5V Low Power Subscriber DTMF Receiver |
| *25 | AD8402/3 | Dual/Quad Digital Pots |
Project Suggestions
In past years, a great variety of projects have been successfully
completed. A list of some completed recently is attached. The
project reports for these are filed in the digital lab.
All the project reports are on file in 38-684. You may sign out any
one for an overnight loan or for reading in the lab. You are free to
make a copy of part or all of a report if you want to keep it for a
longer time. The best and most interesting of your project reports
will be used to augment this list for future terms.
It is often more satisfying to have projects which do something in
addition to blinking LEDs. Examples are audio output, TV monitors,
X-Y displays, X-Y plotters, or VDT terminal displays.
Be careful - most unsuccessful projects were too complex. We will
help you to size your project appropriately.
Last Revised October 29, 1997
This summary provides a concise listing of PAL specifications.
You must refer to individual data sheets for additional details.
Sample architecture specifications are shown for those pals with
programmable architectures. UV erasable pals may be traded at
the instrument room counter for freshly erased ones.
16v8 /c c i ct c c c c
Electrically erasable - simply reprogram it!
This description applies when all outputs are combinational.
Pins 1 - 9 and 11 are dedicated inputs.
Pins 12 and 19 are outputs only, not available as inputs
Pins 13 - 18 are outputs which can also be used as inputs.
All outputs have 7 product terms
and one tri-state enable product term.
All outputs can be inverted or not.
16v8 i /d d c ct /c /c i
Electrically erasable - simply reprogram it!
This description applies when some output is a flip-flop.
Pin 1 is the clock and is not available as an input.
Pin 11 is the flip-flop tristate enable (negative true)
and is not available as an input.
Pins 2 - 9 are dedicated inputs.
Pins 12 - 19 can be combinational or flip-flop.
All outputs can be inverted or not.
All combinational outputs have 7 product terms
and one tri-state enable product term.
All flip-flop outputs have 8 product terms.
20v8 /c ct i c c ct c c
Electrically erasable - simply reprogram it!
This description applies when all outputs are combinational.
Pins 1 - 11, 13 - 14 , and 23 are dedicated inputs.
Pins 15 and 22 are outputs only, not available as inputs.
Pins 16 - 21 are outputs which can be used as inputs.
All outputs have 7 product terms
and one tri-state enable product term.
All outputs can be inverted or not.
20v8 i /dt d c ct /c /c
Electrically erasable - simply reprogram it!
This description applies when some output is a flip-flop.
Pin 1 is the clock and not available as an input.
Pin 13 is the flip-flop tristate enable (negative true).
and is not available as an input.
Pins 2 - 11, 14, and 23 are dedicated inputs.
Pins 15 - 22 can be combinational or flip-flop.
Pins 15 - 22 can be inverted or not.
All combinational outputs have 7 product terms
and one tri-state enable product term.
All flip-flop outputs have 8 product terms.
All outputs can be inverted or not.
ep300 i /cp df dft cct cc /cc /df
UV erasable - exchange it at the instrument room.
Pin 1 is the clock and is also available as an input.
Pins 2 - 9 and 11 are dedicated inputs.
Pins 12 - 19 can be combinational or flip-flop.
All outputs have 8 product terms
\ and one tri-state enable product term.
All outputs can be inverted or not.
There is a common asynchronous clear and
synchronous set for all ff.
16l8
This pal has a fixed architecture.
You can only program it once!
Pins 1 - 9, and 11 are dedicated inputs
Pins 12 and 19 are outputs only.
Pins 13 - 18 are outputs which can be used as inputs.
All outputs have 7 product terms
and one tri-state enable product term.
All outputs are inverted.
16r8
This pal has a fixed architecture.
You can only program it once!
Pin 1 is the clock and not available as an input.
Pin 11 is the flip-flop tristate enable (negative true).
Pins 2 - 9 are dedicated inputs.
Pins 12 - 19 are inverted flip-flops.
All outputs are flip-flops and have 8 product terms.
16r6
This pal has a fixed architecture.
You can only program it once!
Pin 1 is the clock and not available as an input.
Pin 11 is the flip-flop tristate enable (negative true).
Pins 2 - 9 are dedicated inputs.
Pins 13 - 18 are inverted flip-flops.
All flip-flop outputs have 8 product terms.
Pins 12 and 19 are inverted combinational.
All combinational outputs have 7 product terms
and one tri-state enable product term.
16r4
This pal has a fixed architecture.
You can only program it once!
Pin 1 is the clock and not available as an input.
Pin 11 is the flip-flop tristate enable (negative true).
Pins 2 - 9 are dedicated inputs.
Pins 14 - 17 are inverted flip-flops.
All flip-flop outputs have 8 product terms.
Pins 12 - 13 and 18 - 19 are inverted combinational.
All combinational outputs have 7 product terms
and one tri-state enable product term.
22v10 i /c /d dt ct i /c /d dt ct
UV erasable - exchange it at the instrument room.
Pin 1 is the clock and is also available as an input.
Pins 2 - 11 and 13 are dedicated inputs.
Pins 14 - 23 can be combinational or flip-flop.
All outputs can be inverted or not.
All outputs have one tri-state enable product term.
Pins 14 and 23 have 8 product terms.
Pins 15 and 22 have 10 product terms.
Pins 16 and 21 have 12 product terms.
Pins 17 and 20 have 14 product terms.
Pins 18 and 19 have 16 product terms.
There is a common asynchronous clear and
\ synchronous set for all ff.
5c060 i i i i i i i i dfc /dfc /cft cct cct /dc /cct
UV erasable - exchange it at the instrument room.
Pin 1 is the synchronous clock for pins 3 - 10.
Pin 13 is the synchronous clock for pins 15 - 22.
Pins 1 and 13 are not available as inputs.
Pins 2, 11, 14, and 23 are dedicated inputs.
Pins 3 - 10 and 15 - 22 can be combinational or flip-flops.
All outputs can be inverted or not.
All combinational outputs have pin feedback and
one tri-state enable product term.
All flip-flop outputs have an asynchronous clear.
All flip-flop outputs can have either
\ pin or register feedback.
All flip-flop outputs can have either one
tri-state enable product term or
\ an asynchronous clock product term.
All flip-flops can be either D or T flip-flops.
85C220 i /cp df dft cct cc /cc /df
UV erasable - exchange it at the instrument room.
Pin 1 is the clock and is also available as an input.
Pins 2 - 9 and 11 are dedicated inputs.
Pins 12 - 19 can be combinational or flip-flop.
All outputs have 8 product terms
\ and one tri-state enable product term.
All outputs can be inverted or not.
There is a common asynchronous clear and
synchronous set for all ff.
Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science
6.905 SUPPLEMENTAL PROJECT CREDIT
Permission Form for an extra 6 units for 6.111
Written proposals and logic diagram conferences must be
completed by the posted deadlines.
The deadline for registration for extra units is DROP DATE.
Deviations from this deadline will NOT be made.
An ADD card must be filled out. The student is
responsible for securing Prof. Kirtley's signature,
his/her advisor's signature, and delivering the ADD card to the
Registrar on or before DROP DATE.
You must present to Prof. Kirtley the following, at least one day before
DROP DATE:
ADD card for 6 units of 6.905;
Permission Form (this page) signed by your TA;
copy of your Project Proposal.
NOTE: Prof. Kirtley keeps the Permission Form and a copy of your Project Proposal.
You may, if you wish, leave the filled-in paperwork listed in
4. above at the Instrument Room desk at the entrance to the
6.111 lab (38-601). After signing your ADD card, Prof. Kirtley will
leave it there so that you may conveniently get your ADD card and
take it to the Registrar.
Your grade for the extra 6 units will be the same as your 6.111
grade.
The extra 6 units may not be used to satisfy either the
Institute or the departmental lab requirement.
Your Name Course
Class Phone Term
Term Address: No. of Units
Electronic Mail Address
Attach your 6.111 Project Proposal to this Permission Form.
6.111 Instructor's Agreement: The project described above is
suitable for 6 Units of 6.905 credit.
TA Signature Date
Massachusetts Institute of Technology
Department of
Electrical Engineering and Computer Science
6.111 - Introductory
Digital Systems Laboratory
PROPOSAL ABSTRACT FOR TERM PROJECT
(Submit in duplicate jointly with your partner.)
NAME:
(last) (first) (initial)
(Term residence phone)
(Address)
NAME:
(last) (first) (initial)
(Term residence phone)
(Address)
Title of Project (nine words or less):
ABSTRACT
(One paragraph description)
TENTATIVE DIVISION OF WORK
(One paragraph statement of how work is to be divided between
partners.)
Francis Doughty
Wed Oct 29 14:44:04 EST 1997