6.111 Introductory Digital Systems Laboratory

Lab 3 HINTS

The hints below are provided to assist you with some of the details of the lab. These hints are be no means complete. Please consult with a TA whenever you are unsure of anything. Use the design conference to answer any questions you may have during the design phase of the lab. Good Luck!

(1) Start early!!! This lab is larger in size and complexity than Lab 2. This lab will require a FULL TWO WEEKS of effort to be completed. Don't let it slide into the second week before you begin.

(2) Try to keep your wiring as compact as possible. Long wires introduce delays and are more susceptible to analog noise. This is especially important when dealing with your clock. Noise corrupted clock signals account for many of the problems we usually encounter in Lab 3.

(3) Also be careful with the loading of your clock. You may run into trouble if you try to drive every clock signal on your kit from a single output of a 393 counter. Sending the clock through several parallel buffers will help you avoid putting to much load on your clock signals. See Figure 1 attached with these hints.

(4) In Lab 3, you will need to build three clocks in your timing unit. One clock will be your system clock, one clock will control the UART's sampling of the serial line, and the third clock will control your sampling frequency.
The UART clock is required to be 9600x16 Hz or 153.6 kHz. This clock can be easily created by dividing your 1.8432 MHz clock by 12. Examination of the UART's specification sheet reveals that this clock does not need to have a 50% duty cycle (check the spec. sheet for the exact requirements for the clock). You can use this fact to simplify your divider.
When dealing with audio signals, a sampling frequency of at least 8 kHz is generally required to maintain reasonable sound quality for speech and music (CD players use a sample frequency of  44 kHz). You can create your sampling frequency clock by simply dividing down your 9600x16 Hz UART clock. Thus, dividing the UART clock by 16 gives a sampling rate of 9600 Hz. It should be relatively easy to design your system efficiently enough to maintain a sampling frequency of 9600 Hz. You should also be able to compute the largest sampling rate you can use and still have your design work.
In lab 2, your system clock frequency did not have to be large since the computational requirements of the data paths were minimal. In lab 3, your MCU must control a real-time digital filter. If you perform your calculations correctly, you should find that a system clock of 921.6 kHz (i.e. half of 1.8432 MHz) should be adequate for the job, but smaller frequencies may not allow your design to operate in real time. You should verify this result in your lab. You should also verify that the clock speed you use does not violate any of the timing requirements imposed by the chips you use in your design.

(5) The specification sheet for the analog to digital converter offers several different approaches for handling the timing of the device. We recommend that you follow the timing diagram in Figure 2 of these hints. Be sure you understand the various propagation delays of the A2D.

(6) The filters that are provided to you all have a unit gain factor. Thus, the output signal will never exceed the amplitude of the input signal regardless of the input signal's frequency. This fact allows you to build an 8-bit accumulator instead of a 12-bit accumulator.

(7) The first four filters (0 through 3) are provided to help you in debugging your circuit. The first filter is simply a single impulse, therefore the output signal from this filter should be the same as the input signal. The second filter is a negative impulse so its output should be the negative of the input signal. The third filter is a ``box car'' filter. The fourth filter is an ``exponential'' filter. By inputing a square wave into these filters you should get outputs shown in Figure 3. The complete list of the filters is given in Table 1. The filter coefficients are provided in sign-magnitude HEX format. If you are not familiar with sign-magnitude notation a TA can explain it to you.

 

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

h[0] 7F FF 08 20 00 83 00 00 81 03 06 00 88 86 08 00

h[1] 00 00 08 18 00 03 00 01 04 0B 03 8A 88 07 01 87

h[2] 00 00 08 12 82 04 00 00 00 04 8C 0A 00 0A 88 89

h[3] 00 00 08 0E 83 82 00 84 87 86 02 85 0D 8B 0F 1D

h[4] 00 00 08 0A 81 8A 00 05 07 91 10 87 11 87 8D 05

h[5] 00 00 08 08 09 82 00 0A 0B 8E 87 12 06 12 01 08

h[6] 00 00 08 06 18 18 00 A5 A4 03 92 94 8C 03 0E 03

h[7] 00 00 08 04 24 31 40 33 31 14 0E 08 63 65 64 48

h[8] 00 00 08 03 24 31 C0 A5 A4 14 0E 08 8C 03 0E 03

h[9] 00 00 08 02 18 18 00 0A 0B 03 92 94 06 12 01 08

h[10] 00 00 08 02 09 82 00 05 07 8E 87 12 11 87 8D 05

h[11] 00 00 08 01 81 8A 00 84 87 91 10 87 0D 8B 0F 1D

h[12] 00 00 08 01 83 82 00 00 00 86 02 85 00 0A 88 89

h[13] 00 00 08 01 82 04 00 01 04 04 8C 0A 88 07 01 87

h[14] 00 00 08 01 00 03 00 00 81 0B 03 8A 88 86 08 00

h[15] 00 00 08 00 00 83 00 00 00 03 06 00 00 00 06 00