Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 4 - Starting to Implement the Beta February 29, 2000 Revised: March 1, 2000 Issued: March 1, 2000 Design Review : March 6, 2000 Check Off: March 10, 2000 Report: March 13, 2000 Purpose: To provide a memory interface to CPLDs for later beta implementation. Also to provide components useful in a later beta implementation. Design Review The design review exists to provide you timely feedback on the design of the register file. No design review is required for the implementation of any components, the instruction memory, or the data memory. Of course, you may meet with a TA or Professor Troxel in order to discuss any aspect of this lab. Builtin Components Some of the components used in jsim for simulation of the beta are naturally provided by VHDL. These include inverter, buffer, and2, and3, and4, nand2, nand3, nand4, or2, or3, or4, nor2, nor3, nor4, xor2, xnor2, constant0, and constant1. Packaged Components You may code and simulate these components either yourself or in cooperation with other 6.004 option students. All components are to be of length "length" as passed in by a generic map. The default length is 2. I doubt that a length of 1 works as the vector defined would be (0 downto 0), All types are std_logic_vector(length - 1 downto 0) for individual signals which depend on the length and std_logic for all other signals. Desired components include: register inputs d, reset, clk outputs q The reset signal is asynchronous; when it is one then the q output(s) become zero after a delay, but not waiting until the rising edge of clk. The input d is sampled by the rising edge of the clk to form the output q. tristate inputs e and z outputs z z <= a when e = '1' else z <= (others => 'Z'); aoi22 inputs a1, a2, b outputs z z <= not((a1 AND a2) OR b); oai22 inputs a1, a2, b outputs z z <= not((a1 OR a2) AND b); mux2 inputs s, d0, d1 outputs z z <= d0 when s = '0' else d1; mux4 inputs s0, s1, d0, d1, d2, d3 outputs z some sort of case statement - you write it Memory Subsystem There are three memory systems. These are the instruction memory, the data memory, and the register file. The data memory is never written to at the same time that it is read, so the data bus for this memory should be tri-state. Since very few of the instructions are read or write to the data memory, the data busses for the two memories can be a single tri-state bus for economy of pins. If there are enough pins for your beta implementation, then the instruction memory output bus can be separated from the data bus for the read/write memory. It is reasonable for these two memories to share the same addresses if they share an output bus. Perhaps, a control bit can distinguish between the two memories. It is a good idea to block out the implementations of all three memories before starting the wiring of any of them so as to avoid any rewiring and editing of pin_number attributes in your vhdl files. Instruction Memory. This is perhaps the simplest of the memory units as it reads a prom. As previously stated, a control bit can be used as the output enable for the prom. It is suggested that this memory unit be implemented as a byte read initially. After this is deemed working then the cpld code can be enhanced to do the four-step required to do a 32 bit read. Testing of the instruction memory is best done with a prom programmed with a known sequence, such as FF 00 AA 55, with another section of the prom programmed with the same pattern for 32 bit words. It is likely a good idea to use eight bits which are then to be displayed on the hex leds on the switches and lights board in conjunction with a push button switch to cycle through the addresses. Of course, it might be a good idea to display the addresses on other hex leds. I suspect that you can use the leds on the switches and lights board in the kit and it is not necessary to use separate hex leds. Minimize wiring when you can. Read/Write Memory This memory (at least initially) shares its addresses and data busses with the instruction memory. A good way to test this memory is to use the prom as a data source and to write, then read the ram comprising the read/write memory. Naturally, you should get an error if you physically remove the memory or ground (remove the wire first!) the output enable. Be careful, tri-state busses tend to hold the last value on the bus even when nothing is driving the bus. (It is dangerous when the road curves when no one is driving the bus.) Register Memory In the beta, the register file has two separately addressable outputs. We do not have any dual addressable register files available. However, you can use a trick first implemented by Data General (as far as I know) that uses two register files. The trick is to write the same data to both register files simultaneously. That way one can read out different (or the same) registers and always have the correct output data. It is desirable for the register memory to have a separate input bus and two separate output busses. However, we do not have clocked rams. Instead they can either be read or written. Since the cpld is considerably faster than the rams, it is likely better to implement the sequence of read and write operations by an fsm in the cpld. This would then take eight clock ticks to do a register read or write. This makes the register memory more complicated. Higher performance would result if we were to purchase edge triggered register memories. We can do this, but we have to get on with the implementation and likely cannot suffer the time delays involved with such a purchase. Do you want to write before you read or read before you write? Remember, the last thing that happens in the beta is the writing of the result back into the register file. This memory requires five address bits for each register file to specify the register being read or written. If two rams are used then each is addressed by five bits of address and each has an eight bit IO bus. It is likely reasonable to let the cpld distinguish whether r31 is being addressed and interpret the data reported.