6.111 Q2-review.1 April 5, 2000

Quiz 2

• Friday, April 7, 2000, 12:00 - 1:00 (Class Time)
• Room 50-340 (Walker)
• 2 handwritten crib sheets allowed.

General Topics:

• Finite State Machines:
  • State Description
  • Transition Tables
  • Implementation in hardware
  • Finite State Machine Compiler
• PAL's and CPLD's
  • e.g. 22v10, CYC374I
  • Product Terms (and their limits)

• VHDL
  • Entity Declaration
  • Architecture Specification
  • Process to wrap around concurrent statements
  • Assignments and logical statements
  • if-then, elsif-then, else, endif
  • case-when-end case
  • How to code FSM's
• Memory
  • SRAM: (e.g. 6116)
    • Read/Write functions
    • Chip Enble
    • Write Pulse
  • ROM (e.g. 28F256A Flash Memory)

6.111 Q2-review.2 April 5, 2000

• Microcoded Control Units (MCU's)
  • Vertical and Horizontal 1-Instruction microcoding.
  • 2-Instruction Machines:
    • Use of counter (e.g. '163) as sequencer
    • Use of MSB to distinguish Assert and If Cond Then Jump
    • Expansion to multiple instructions
  • Chips to be familiar with:
    • MSI stuff: AND, OR, NAND, NOR, XOR,...
    • Clocked D, J-K flip flops and registers
    • '163, '169 and '393 counters
    • '151 MUX and '138 Decoder
    • '95 and '194 Shift Registers
    • '85 digital comparator
    • 6116 SRAM and 28F256A Flash Memory
    • PAL's (e.g. 20v8 and 22v10)
    • CYC374I

6.111 Q2-review.3 April 5, 2000

DESIGN RULES

1. Use modularity:
   • Small subsystems are simpler to design
   • Subsystem definition is important
2. Design for testability:
   • Design subsystems so they will run alone
   • Design in break-points
3. Use Don't Cares to simplify combinational logic.
   • Avoid trap states (check use of Don't Cares).
   • Decade counters and other FSM's may have strange sequences for illegal states.
4. Do your logic design carefully, and first:
   • Make up block (functional) and circuit diagrams (with pin numbers)
   • Use logic symbols appropriate to algebraic representation
   • Use names appropriate to assertion level.
5. Avoid problems from ``glitches'':
   • Gate delays can (and do) cause ``glitches''.
   • Satisfy (current) loading rules.
   • Glitch-free combinational logic requires (but is not guaranteed by) single input changes.
   • CLK, G, /PR and /CL inputs must NOT have glitches.
   • Carry from counter (e.g. 163) can have glitches.
   • Don't gate the clock.
   • Be sure that combinational output is stable before assertion of clock.
6. Use proper timing:
   • Clock period Max (FF delay,Input Changes) + CL delay + Setup.
   • Obey flip-flop timing restrictions: setup, hold times, clock width.
   • Don't derive asynchronous clear from flip-flops to be cleared.
   • All edge-triggered flip-flops must operate on the SAME clock edge.
   • Beware of clock skew.
   • Tree structure to expand clock.
   • Change inputs only (just) after the clock edge.

   6.111 Q2-review.4 April 5, 2000
   

7. Be careful about asynchronous events:
   • Synchronize all external inputs.
   • Asynchronous event should change ONLY one flip-flop.
   • Consider pulse width carefully (does your application need a narrow pulse or a sustained level?)
   • Beware of bouncing switches!
   • Use monostables sparingly.
8. Be careful of multi-ended wiring paths:
   • Avoid tri-state bus contention.
   • Account for turn-off delays.
   • Don't overload outputs (observe fan-out)
9. Use memory properly:
   • Avoid High-Z address to SRAM when CE is true.
   • Avoid address changes when write pulse is true.
   • Make sure your write pulse is ``clean''.
10. Wire properly:
    • Keep wires short.
    • Wire all inputs (even unused ones).
    • Use bypass (decoupling) capacitors.
    • Use multiple grounds between kits.
    • Alternate ground with signals in flat cables.
    • Use twisted pairs between kits.
    • Don't overload your power supply!
11. Use debugging strategy:
    • Short test programs
    • Debug modules systematically
    • Check for power supply and ground on every chip
    • Is every pin wired? Why not?
    • Thermal de-bugging may help with bus contention.
    • Use a `scope! Check valid logic levels and power supply.
    • Use your logic analyzer for checking sequencing.