Last Revised  6 Mar 2000

This outline is dynamic.  The only thing about it that is unlikely
to change much is that which has already happened.

All lectures (not quizzes) have lecture notes in addition to the
handouts listed below.

L1 W	 2 FEB	First Day Packet-includes:	Overview, Boolean Algebra
		  Lecture notes (part)		Intro to VHDL
		  General Information
		  Due Dates
		  Computer Information
		  Intro to HP Logic Anal.
		  Beginner's Guide to WARP
		  PS 1, Lab 1
		  Safety memo
		  Kit sign-out sheet
		  6.111 Sign-up sheet

L2 F	 4 FEB	Gates, Symbols, and Busses	Symbols, Kmaps,
		Kmap				TTL Innards
		(not option)			Ring Oscillators
						Latches, Edge Trig. FF
						D, T, SR, JK flip-flops
						Computer Demo

L3 M	 7 FEB					VHDL entities
						VHDL architectures
						Structural Ckt. Diag
						Output Eqns in report
						VHDL Statements
						Computer Demo
						VHDL simulation

L4 W	 9 FEB	Pal Programming			PALs (PLD)s
		PS 2, PS 1 Solutions		Programming PALs and CPLDs
		Negative True			VHDL and Negative True
		CPLD Programming

L5 F	11 FEB	(not option)			MUXes, Counters, Shift Reg.
						FSM Notation
						FSM example

L6 M	14 FEB	Lab 2				VHDL statements
						VHDL processes
						Generic and Others
						VHDL counters
						Counter simulation
						Computer Demo

L7 W	16 FEB	PS 3, PS2 Solutions		Pulse Synchronization
						Lab 2 Discussion
						Lab 2 Demo (TV camera)

L8 F	18 FEB	Report Guide			Memories
						FSMs in VHDL
						Mary Zoll Phase II

L9 T(M)	22 FEB					Grid Example
						Tri-state and VHDL
						VHDL identifiers,

L10 W	23 FEB	PS 3 Solutions			finish Grid Example
						Q1 review
						

Q1  F	25 FEB	(not option)			Quiz I in 34-101

    F	25 FEB	(option)			Beta implementation
						strategy - in lab

L11 M	28 FEB	PS 4				Implied adders, Packages
						Simulation details
						Computer Demo

L12 W	 1 MAR	Lab 4 (option)			Lab 4 and 5 Discussion

L12.5 F  3 MAR					Microprogramming,
						Trolley Car Example

L13 M	 6 MAR	Prom Guide			Finish Trolley Car Example
						Prom programming

L14 W	 8 MAR	PS 5, PS 4 Solutions		Lab 3 Discussion
		Lab 3 (not option)		Lab 3 Demo (TV camera)

L15 M   13 MAR  Lab 5				VHDL Summary

L16 W	15 MAR					Opamps, D2A, A2D
                                                A2D Aliasing Demo

L17 M	27 MAR	PS 5 Solutions			Project Kickoff
		Project Info			Video tape

L18 W	29 MAR					Video I

L19 M	 3 APR	MC 6847				Video II
                                                Transmission Lines

L20 W	 5 APR	How to make your project	Motors
		work				Q2 review

Q2  F	 7 APR					Quiz 2 in 50-340

    W   19 APR					Project Design Presentations
	        Last day to get your add card for 6 units of 6.905 signed

    Th  20 APR	Drop Date
                Last day to deliver add card to the registrar's office

    F   21 APR					Project Design Presentations

    M   24 APR					Project Design Presentations

    W   26 APR					Project Design Presentations

    F   28 APR					Project Design Presentations

    W   10 MAY					Demos and Video Taping

    Th  11 MAY					Project Reports due by 5 PM