Last Revised  6 April 1999

This outline is dynamic.  The only thing about it that is unlikely
to change much is that which has already happened.

All lectures (not quizzes) have lecture notes in addition to the
handpouts listed below.

L1 W	 3 FEB	First Day Packet		Overview, Boolean Algebra
		Lecture notes
		General Information
		Due Dates
		Computer Information
		Intro to HP Logic Anal.
		Beginner's Guide to WARP
		PS 1, Lab 1
		Safety memo
		Kit sign-out sheet
		6.111 Sign-up sheet

L2 F	 5 FEB	Gates, Symbols, and Busses	Symbols, Kmaps,
		Kmap				TTL Innards
		Negative True and VHDL		Static Hazzards
						Computer Demo

L3 M	 8 FEB					Ring Oscillators
						Latches, Edge Trig. FF
						D, T, SR, JK flip-flops
						VHDL entities
						Ckt. Diag. vs Architecture
						Output Eqns in report
						Computer Demo

L4 W	10 FEB	Pal Programming			PALs (PLD)s
		PS 1 Solutions, PS 2		Programming PALs

L5 F	12 FEB					MUXes, Counters, Shift Reg.
						VHDL processes, VHDL
						163, Simulation
						Computer Demo

L6 T(M)	16 FEB	Lab 1 due			FSM Notation, FSMs in VHDL

L7 W	17 FEB	Lab 2				Pulse Synchronization
		PS2 Solutions, PS 3		Lab 2 Discussion

L8 F	19 FEB	Report Guide			Memories
		6264 Data Sheets		Lab 2 Demo (TV camera)
		2 handouts on phase II		Mary Zoll Phase II

L9 M	22 FEB					Grid Example, VHDL identifiers,
						concurent statements

L10 W	24 FEB	PS 3 Solutions			VHDL sequential statements
		Lab 2 Design Checkoff		Tri-state, Q1 review
						finish Grid Example
						2 Vugraph projectors

Q1 F	26 FEB					Quiz I in 2-190

L11 M	 1 MAR	PS 4				Implied adders, Packages
						Simulation details
						Computer Demo

L12 W	 3 MAR					Microprogramming,
						Trolley Car Example
						2 Vugraph projectors

L13 M	 8 MAR					Finish Trolley Car Example
						2 Vugraph projectors

L14 W	10 MAR	PS 4 Solutions, PS 5		Prom programming, Lab 3
		Lab 3, Lab 2 Checkoff

    F   12 MAR  Lab 2 Report Due

L15 M	15 MAR	Lab 3 MCU Checkoff		Opamps, D2A, A2D

L16 W	17 MAR	Lab 3 Design Checkoff		Project Kickoff
						Video tape

    F   19 MAR	PS 5 due in lab

L17 M	29 MAR	PS 5 Solutions			VHDL Summary
		Project Abstracts Due		Guest Lecturer (Prof.
						Anantha Chandrakasan
						Low Power

L18 W	31 MAR					Video

    F    2 APR  Lab 3 Checkoff

L19 M	 5 APR	Lab 3 Report Due		Transmission Lines, Motors
		How to make your project	Scope + TV camera
		work

L20 W	 7 APR					Q2 review
						Guest Lecturer (Yonald Chery)

Q2  F	 9 APR					Quiz 2 in 2-190

  M-F  5-9 APR	Proposal Conferences

 M-F 12-16 APR	Block Diagram Conferences

    W   21 APR					Project Design Presentations
        Last day to get your add card for 6 units of 6.905 signed

    Th  22 APR	Drop Date
                Last day to deliver add card to the registrar's office

    F   23 APR					Project Design Presentations

    M   26 APR					Project Design Presentations

    W   28 APR					Project Design Presentations

    Th  30 APR					Project Design Presentations

    W   12 MAY		Demos and Video Taping

    Th  13 MAY		Project Reports due by 5 PM