Slide 1: Overview of our design process
Slide 2: Steps required to get started in Powerview
Slide 3: What to do with finished code
Slide 4: Block diagram of design
restart stepsize 15ns radix hex /cache_out radix hex /cpu_adr radix hex /mem_data wave wave cache.vcd /init /ce /cpu_adr /cache_ready /cache_out /line0 /line1 /line2 /line3 /get_data /mem_ready /mem_data wfm /init @0ns = 0 @10ns = 1 @40ns = 0 wfm /ce @0ns = 0 @90ns = 1 @150ns = 0 @250ns = 1 @450ns = 0 @550ns = 1 @750ns = 0 @840ns = 1 @900ns = 0 wfm /cpu_adr @0ns = zz\h @80ns = 00\h @150ns = zz\h @240ns = 81\h @450ns = zz\h @540ns = 82\h @750ns = zz\h @830 = 81\h @900ns = zz\h wfm /mem_ready @0ns = 0 @350ns = 1 @400ns = 0 @650ns = 1 @700ns = 0 wfm /mem_data @0ns = zz\h @340ns = 81\h @400ns = zz\h @640ns = 82\h @700ns = zz\h sim 980ns
Another useful command to know is
clock /clock 1 0
The clock transitions on the step size, so in the code above, the clock would start high at 0ns, then transition low at 15ns, for a 30ns clock period.
Questions about Powerview? Send e-mail to
Daniel Lee (omega@mit.edu) or
Chia (Janet) Wu (janetwu@mit.edu)
971117 dtl