Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science
6.195 - How to Really Design Digital Systems

Project 1 Assigned - October 23, 1997

Due : November 13, 1997
Class presentations start November 13, 1997

Reading

Assigned Text on VHDL

Chapter 8

Project 1 - Learning how to use the tools

Choose some aspect of a Mentor or Viewlogic tool. The basic idea is that you and others will use these tools in the conduct of project 2 which is the last major assignment. All project reports are to be in web page format. My secretary, doughty@mit.edu, will assist you in converting to html format as you desire. Acceptable inputs are:
plain text
latex
framemaker
html
There may be other formats, contact Fran Doughty for details if desired.

Anything that prepares one for the final project is acceptable. Other ideas may be acceptable. I will have office hours at class time when we have no classes. We will not have any classes until November 13, 1997. The two or three classes starting November 13, 1997 will consist of verbal presentations of project 1. You may use vugraphs, chalk, or handouts. There will be an optional demonstration to occur near the end of class in the digital lab - 38-600 on either sunpal[12] or the HP machines (as you wish).

The final project will involve showing that your design works by simulation. An acceptable project 1 is therefore a method of simulation of your behavioral VHDL description prior to actual fitting of your code to actual devices. For example, use the Viewlogic Speedwave tool to simulate behavioral VHDL code.

Notification of any deviation in class schedules or instruction will be via email to 6.195students@mit.edu